The Internet of Everything: What's Missing?
Wireless technology has evolved through three distinct ages. A fourth age -- the Internet of Everything -- is poised to explode and take us to terascale connectivity. But one trillion is a huge, almost incomprehensible number. It is so huge, in fact, that scaling presents both a qualitative and quantitative challenge. Are there enough engineers to design all of these devices? Will the economics of making chips have to change fundamentally? How are we going to provide power for all of these things? Do we need new protocols and standards? How about circuits? This talk will consider impediments to achieving the terascale and what engineers should be thinking about now to make sure that we can get to the terascale sooner than later.
Thomas Lee received his degrees from MIT, where his 1989 thesis described the world's first CMOS radio. He has been at Stanford since 1994, having previously worked at Analog Devices, Rambus and other companies. He's helped design PLLs for several microprocessors (notably AMD's K6-K7-K8 and DEC's StrongARM), and has founded or cofounded several companies, including the first 3D memory company, Matrix Semiconductor (acquired by Sandisk), and IoE companies ZeroG Wireless (acquired by Microchip) and Ayla Networks. He is an IEEE and Packard Foundation Fellow, has won "Best Paper" awards at CICC and ISSCC, was awarded the 2011 Ho-Am Prize in Engineering and an honorary doctorate from the University of Waterloo. He is on the board of Xilinx, served as Director of DARPA's Microsystems Technology Office, holds ~60 patents, and authored several textbooks. He owns 150-200 oscilloscopes, thousands of vacuum tubes, and kilograms many of obsolete semiconductors. No one, including himself, quite knows why.
Giovanni De Micheli
New trends is electronic systems: Technology, circuits and architectures
This talk will address the needs of new emerging technologies, such as 2-dimensional nanoelectronics, optical devices and quantum devices in terms of design support through computer aids. I will present the circuit abstractions, as well and design methods to achieve competitive circuits.
I will show where existing tools and flows can be used and where new algorithms and data structures are needed in the search of the best match between devices and architectures. I will conclude with some examples of emerging designs.
Giovanni De Micheli is Professor and Director of the Institute of Electrical Engineering and of the Integrated Systems Centre at EPF Lausanne, Switzerland. He is program leader of the Nano-Tera.ch program. Previously, he was Professor of Electrical Engineering at Stanford University.He holds a Nuclear Engineer degree (Politecnico di Milano, 1979), a M.S. and a Ph.D. degree in Electrical Engineering and Computer Science (University of California at Berkeley, 1980 and 1983).
Prof. De Micheli is a Fellow of ACM and IEEE, a member of the Academia Europaea and an International Honorary member of the American Academy of Arts and Sciences. His research interests include several aspects of design technologies for integrated circuits and systems, such as synthesis for emerging technologies, networks on chips and 3D integration. He is also interested in heterogeneous platform design including electrical components and biosensors, as well as in data processing of biomedical information. He is author of: Synthesis and Optimization of Digital Circuits, McGraw-Hill, 1994, co-author and/or co-editor of eight other books and of over 800 technical articles. His citation h-index is 93 according to Google Scholar. He is member of the Scientific Advisory Board of IMEC (Leuven, B), CfAED (Dresden, D) and STMicroelectronics.
End of CMOS miniaturization and technology development after that
Recent smart society has been conducted by the progress of semiconductor technologies, especially by that of CMOS miniaturization. However, it is afraid that the CMOS miniaturization will reach its limit substantially in several years. However, semiconductor technology development will continue in future after that. In this talk, the limit of the CMOS miniaturization is explained and the semiconductor device technology development after reaching the scaling limit is discussed.
Prof. Hiroshi Iwai is a Professor Emeritus, Tokyo Institute of Technology, Yokohama, Japan.
He is a semiconductor device engineer who received BE and Ph.D degrees from Univ. of Tokyo. He worked at Toshiba for 26 years from 1973 and at Tokyo Institute of Technology for 20 years since 1999, engaged in the development of high-density memories and logic/RF/photovoltaic/power devices.
Especially, he has contributed to the miniaturization of MOSLSI devices. Also, he has been concentrated to the development of Si and GaN power device
technologies for these 10 years.
He is a life fellow of IEEE and served as an IEEE EDS president and a Division I Director, and served as an IEEE EDS Distinguished lecturer for 25 years since 1994.
Subramanian S. Iyer
A Moore’s law for Packaging
While Silicon has scaled aggressively by over a factor of a few thousand over the last six decades the progress in packaging has been more modest – a linear factor 4-5 in most cases. In this talk, we will examine the reasons for this lag and what we are doing to fix this imbalance. Packaging is undergoing a renaissance where chip-to-chip interconnects can approach the densities of on-chip interconnects. We will discuss the technologies that are making this happen and how these can change our thinking on architecture and future manufacturing. Specifically, we will discuss two embodiments: Silicon as the next generation packaging substrate, and Flexible electronics using fan-out wafer level processing. Finally, we’ll
discuss how these developments can help put some intelligence into Artificial Intelligence and bring about change in Medical Engineering.
Subramanian S. Iyer (Subu) is Distinguished Professor and holds the Charles P. Reames Endowed Chair in the Electrical Engineering Department and a joint appointment in the Materials Science and Engineering Department at the University of California at Los Angeles. He is Director of the Center for Heterogeneous Integration and Performance Scaling (CHIPS). Prior to that he was an IBM Fellow. His key technical contributions have been the development of the world’s first SiGe base HBT, Salicide, electrical Fuses, embedded DRAM and 45nm technology node used to make the first generation of truly low power portable devices. He also was among the first to commercialize bonded SOI for CMOS applications through a start-up called SiBond LLC. He has published over 300 papers and holds over 70 patents. He was a Master Inventor at IBM. His current technical interests and work lie in the area of advanced packaging constructs for system-level scaling and new integration and computing paradigms as well as the long-term semiconductor and packaging roadmap for logic, memory and other devices. He has received several outstanding technical achievements and corporate awards at IBM. He is an IEEE Fellow, an APS Fellow and a Distinguished Lecturer of the IEEE EDS and EPS as well as it treasurer of EDS and a member of the Board of Governors of IEEE EPS. He is also a Fellow of the National Academy of Inventors. He is a Distinguished Alumnus of IIT Bombay and received the IEEE Daniel Noble Medal for emerging technologies in 2012.
Total Citations:11446 (google scholar)
H-Index: 57 (google scholar)
Adrian M. Ionescu
Energy efficient computing and sensing in the Zettabyte era: silicon to the cloud
Abstract— In this talk we present and discuss some of the great research challenges and opportunities related to 21st century energy efficient computing and sensing devices and systems, in the context of the Internet of Things (IoT) revolution. In the future, major innovations will require holistic approaches encompassing silicon and cloud technologies and will be centered on big/abundant data and context. There is still an important role to be played by innovations in energy efficient technologies, devices, and system design, building on the success of silicon CMOS. Overall, the predicted future global amounts of stored, computed, communicated, and sensed information will certainly challenge the world capability to process and make sense of zettabytes of data, requiring orders of magnitude improvements in energy efficiency. We will discuss the challenges of edge, neuromorphic and quantum computing and we will show that they are rather complementary and will co-exist as part of future digital computing platforms.
Adrian M. Ionescu is a Professor at the Swiss Federal Institute of Technology, Lausanne, Switzerland. He received the B.S./M.S. and Ph.D. degrees from the Polytechnic Institute of
Bucharest, Romania and the National Polytechnic Institute of Grenoble, France, in 1989 and 1997, respectively. He has held staff and/or visiting positions at LETI-CEA, Grenoble, France, LPCS- ENSERG, Grenoble, France and Stanford University, USA, in 1998 and 1999.
Dr. Ionescu has published more than 400 articles in international journals and conferences. He received many Best Paper Awards in international conferences, the Annual Award of the Technical Section of the Romanian Academy of Sciences in 1994 and the Blondel Medal in 2009 for remarkable contributions to the progress in engineering sciences in the domain of electronics.He is the 2013 recipient of the IBM Faculty Award in Engineering. He served the IEDM and VLSI conference technical committees and was the Technical Program Committee (Co)Chair of ESSDERC in 2006 and 2013.
He is director of the Laboratory of Micro/Nanoelectronic Devices (NANOLAB). He is appointed as national representative of Switzerland for the European Nanoelectronics Initiative Advisory Council (ENIAC) and member of the Scientific Committee of CATRENE. Dr. Ionescu is the European Chapter Chair of the ITRS Emerging Research Devices Working Group.
Energy Efficient Resilient and Adaptive Circuits
Resilient and adaptive circuit techniques enable architectures that are tolerant to static and dynamic variations such as process variation, voltage droops, temperature and aging. These circuit techniques are key to reducing voltage, temperature and reliability guardbands. Guardbands are used to guarantee that systems will operate correctly on the field when subjected to variations under different workloads and operating environments. However, guardbands incur in significant loss in performance, energy efficiency and also impact the reliability of the system.
In this tutorial we will explore resilient circuit techniques used in modern microprocessors and SoCs. We will start by breaking down the different components of the guardband stack and follow up with a discussion of resilient circuits that mitigate them. We will cover resilient circuit techniques from in-situ detection and correction sequential logic to embedded critical path replica circuits to monitor timing margin. In addition, we will analyze recent advances in adaptive clocking systems and guardband-aware voltage regulation control systems.
Carlos Tokunaga is a Senior Staff Research Scientist and leads the Reliability and Resiliency Circuit Technology Group at the Circuit Research Laboratory at Intel Corporation.
Carlos received the B.S. degree in electronics engineering from the University of Los Andes, Bogotá, Colombia, in 2001, and the M.S. and Ph.D. degrees in electrical engineering from the University of Michigan, Ann Arbor, MI, USA, in 2005 and 2008, respectively. He is currently an IEEE Senior Member.
He has served in the Technical Program Committees of GLSVLSI, ISLPED, HOST, CICC and VLSI Symposium. He has published over 40 technical papers in refereed conferences and journals and has received 13 patents.
Non-volatile Storage Controllers
This tutorial will provide an overview of the key design considerations and architectural implementations for controllers used for non-volatile storage. We will begin with a brief overview of the different classes of non-volatile storage devices, including magnetic hard drives, flash memory, and emerging non-volatile memory.
An objective in the design of a controller is to provide the host computer with a simplified interface to the device. This requires that the designer understand the underlying characteristics of the storage media, and implement a set of algorithms to hide the complexity of the media programming and retrieval. We begin this process by discussing the characteristics of Flash NAND storage, including the organization of the Flash NAND die, the storage and retrieval of multiple bits per memory cell, as well as the wear, ageing, thermal effects, and error coding and correction (ECC). From there, we explore the industry transition from 2D to 3D chip architecture and its implications on device complexity.
The next step in the controller design exploration is the logical to physical translation layer that permits us to re-arrange the data within the device. We then discuss the design of the controller system-on-a-chip (SOC) including processor hierarchies, parallelism of operations, queuing and automation. Next, we cover the internal datapath for read and write operations, and we review the role of several peripherals in the controller system. We close with an overview of the host interface characteristics.
Moving on from Flash Memory, we will review three emerging non-volatile memory classes: phase change memory (PCM), resistive RAM (RRAM), and magnetoresistive RAM (MRAM). The write-in-place nature of these memory types along with the small access sizes, introduce several architectural differences, which we describe further. Finally, we discuss the new host interface protocols under development for these new memories.
We close the tutorial with an overview of industry trends, and projections for future growth.
Mike Moser is a Senior Technologist at Western Digital Corporation in Milpitas, CA, USA. He has over 30 years’ experience in the storage industry, the last ten of which have been in the architecture of Solid State Drives (SSDs) and storage systems. He led the architecture team responsible for the recently announced Western Digital Black NVMe SSD, and participated in the partnership between SanDisk and HP Enterprise to develop emerging memory devices. His most recent work is on the design of Computational Storage systems.
Mike has a Ph.D. in Applied Mechanics from Caltech, and an Sc.B. in Mechanical Engineering from Brown University. He completed his high school in Bogotá, Colombia and is fluent in Spanish.
Márcio Cherem Schneider
Modeling and design of ultra-low-voltage CMOS circuits
Ultra-low-voltage (ULV) circuits have gained considerable attention in recent years because of the emergence of small batteries and self-powered applications.
Theoretically, the minimum supply voltage for the proper operation of a CMOS inverter is 2 (ln2) (kT/q) = 36 mV at room temperature. In this tutorial we analyze both the CMOS inverter and the Schmitt Trigger circuit in weak inversion operation, and discuss circuit techniques to approach the theoretical low voltage limit.
For analog circuits the minimum supply voltage has been usually considered higher than the minimum necessary for the operation of digital circuits. In this tutorial, we will present analog circuits such as rectifiers and oscillators that can operate from supply voltages below (kT/q).
Essential to the design of ULV circuits is an understanding of the transistor model and the meaning of its main parameters. We will review ultra-low-power circuits that allow the automatic extraction of the specific current IS and the threshold voltage VT of MOS transistors, which are fundamental parameters for circuit design and testing, as well as for technology characterization.
In the lecture we will discuss key issues for ULV circuits, such as MOS transistors with near zero threshold voltage, process and temperature variation of transistor parameters, and modeling features. A minimalistic ULV standard cell family and a section on ULV circuits for energy harvesting are also included.
studied engineering sciences at the University of the Republic, Montevideo, Uruguay, and electronic engineering at the National Polytechnic School of Grenoble (INPG), France. He received an engineering degree in electronics in 1979 and a doctorate degree in 1982, both from INPG. From 1982 to 1989 he was with the University of São Paulo, Brazil. Since 1990, he has been with the Electrical Engineering Department, Federal University of Santa Catarina, Florianópolis, Brazil where he is now a professor. In the second semester of the academic year 1997/98 he was a research associate with the Analog Mixed Signal Group, Texas A&M University. In the academic year 2008/09 he was a visiting scholar at UC Berkeley.
Márcio Cherem Schneider
received the B.E. and M.S. degrees in electrical engineering from the Federal University of Santa Catarina (UFSC), Brazil, in 1975 and 1980, respectively, and the Ph.D. degree in electrical engineering from the University of São Paulo, São Paulo, Brazil, in 1984. In 1976 he joined the Electrical Engineering Department of UFSC, where he is now a Professor. In 1995, he spent a one-year sabbatical at the Electronics Laboratory of the Swiss Federal Institute of Technology,Lausanne. In 1997 and 2001, he was a Visiting Associate Professor at Texas A&M University.
Low-Power Low-Voltage Tamper Detection Circuits
Tamper detection is the ability of a device to sense that an active attempt to compromise the device integrity or the data associated with the device is in progress; the detection of the threat may enable the device to initiate appropriate defensive actions. The tamper detection design can be implemented to sense different types, techniques, and sophistication of tampering, depending on the perceived threats and risks. The methods used for tamper detection are typically designed as a suite of sensors each specialized on a single threat type, some of which may be physical penetration, hot or cold temperature extremes, input voltage variations, input frequency variations, x-rays, and gamma rays. The utility of this technology goes without saying; preventing the theft or damage of assets is obviously critical, and businesses should take appropriate steps to ensure that their assets remain in good condition.
In this tutorial we will describe tamper detection techniques and IC countermeasure circuit architectures. We will review tamper mechanisms covering tamper resistance, tamper evidence, tamper detection and tamper response. Tamper mechanisms are most effectively used in layers to prevent access to any critical components. They are the primary facet of physical security for embedded systems and must be properly implemented to be successful. From the designer's perspective, the costs of a successful attack should outweigh the potential rewards. Additionally, we will focus on a system to effectively detect and prevent illegal use of a MCU out of the specified voltage, temperature, and crystal oscillator frequency ranges. The attacker may drive the MCU above and below the specified ranges of power supply, temperature, and crystal oscillator clock frequency. Once one of these variables is detected to be out of range, a correspondent flag is set to signalize the MCU the potential attack. Then, the MCU may take an action to enhance the overall system security. Circuit architecture and design details are shown in this tutorial.
Alfredo Olmos was born in Cali, Colombia, in 1963, and graduated in Electrical Engineering from Valle University, Colombia, in 1989. During 1988–1990 he worked as a design engineer at the Microelectronics Laboratory of the Valle University. In 1993 he received the MSEE degree (with honors) from the University of São Paulo, Brazil. From 1995 to 1996 he was at Fujitsu Laboratories, Japan, where he developed a 4 GSps Sigma Delta Modulator using HEMT devices. In 1998 he received his Ph.D. degree from the University of São Paulo. From 1998 to 1999 he was Assistant Professor at the Industrial University of Santander, Colombia. From 1999 until 2012 he was working joint to the Analog IP Design team of Freescale Semiconductor Inc. From 2013 to 2017 he was acting as Design manager at Ceitec Semiconductors, in Brazil. Nowadays, Dr. Olmos works as Analog Consulting Engineer. Dr. Olmos holds 28 US patents, 8 Brazilian patents, 2 Europe patents, 1 China patent, and has written more than 50 technical articles as well as several application notes.
Modeling Power Intent through Unified Power Format (UPF, IEEE-1801)
Multi Voltage requirements of complex Systems on a Chip have imposed challenges to IC and IP providers. This lead the Industry to the development of what today’s is a fairly established IEEE standard for modeling these characteristics. Specifically, the standard defines the syntax and semantics of a format used to express power intent in energy-aware electronic system design. Power intent includes the concepts and information required for specification and validation, implementation and verification, and modeling and analysis of power-managed electronic systems. This tutorial will cover the main features provided by the standard and walkthrough a real use scenario in order to showcase how these can be applied to novel designs.
Ronald is an Electronics Engineer from Universidad de Concepción (Concepción, Chile), he also holds a Graduate Certificate on Electronic Circuits from Stanford University (Stanford, CA). He currently manages a team of Application Engineers (A.E.) at Synopsys. The team specialize in Multi Voltage Implementation Tools and Methodologies, covering optimization during Logic Synthesis and Place & Route. As A.E. he provides technical support to field engineers regarding tool and low power methodologies using Synopsys products, they also ensure product quality by performing functional tests using industrial design flows and they collaborate with developers to define requirements for product enhancements.
Bulk Linearization Techniques
Bulk degeneration completes the three basic techniques of linearizing the MOS transistor, the two others are source and gate degeneration. But while source degeneration is very frequent to enhance the performance of several analog circuits, and gate degeneration has been known for a long time, the bulk linearization of a MOS differential pair was only introduced in 2007. At the present a few circuits have been reported using bulk linearization of the MOS transistors to implement high performance transconductors, micro and a nano-power Gm-C filters and amplifiers,and recently compact and highly linear MOS pseudo-resistors. A very interesting result is a minimum in the third harmonic distortion as a result of bulk linearization.
In this tutorial the bulk linearization of the MOS transistor is firstly presented and then analyzed in depth. First the basic concepts of source, gate, degeneration to enhance the linearity of a MOS differential pair are presented, and then the bulk degeneration is introduced. The state of the art in the theory, circuits, and measurements is presented. Then the bulk linearization of the MOS transistor in the triode region, allowing to implement compact and highly linear MOS pseudo resistors is discussed, as well as a bulk-linearized MOS composite transistor. Finally, several application circuits are discussed including nano-power biomedical filters and amplifiers, linear oscillators (AGC and limiting oscillators will be compared), and RF circuits.
Alfredo Arnaud received his PhD, and MSc in microelectronics from Universidad de la República, Montevideo – Uruguay, in 2000 and 2004 respectively. Since 2004 he joined Electrical Engineering Department at Universidad Católica del Uruguay, where he started DIE research group
. Dr. Arnaud holds two patents and as an academic he published more than 80 papers in international journals and scientific meetings and participated in 18 funded R&D projects. Dr Arnaud is the co-founder of two technology companies: Alassio SA in 2004
dedicated to electronics & SW development for POS, medical, RFID devices & traceability within de agribusiness industry among others, and Chipmate in 2009
a spin-off of the DIE aimed at the design of application specific integrated circuits for medical devices and others. For the industry, Dr. Arnaud participated in design and consultancy in the field of microelectronics for implantable medical devices in five different occasions for companies in Uruguay, Brazil, Canada, and India. Dr. Arnaud also participated in the development of embedded electronics like portable POS equipment, a USB dynamic scale for medical applications, and a portable RFID reader according to ISO11784/11785 standard. He is currently IEEE-CAS chapter chair in Uruguay.