The Internet of Everything: What's Missing?
Wireless technology has evolved through three distinct ages. A fourth age -- the Internet of Everything -- is poised to explode and take us to terascale connectivity. But one trillion is a huge, almost incomprehensible number. It is so huge, in fact, that scaling presents both a qualitative and quantitative challenge. Are there enough engineers to design all of these devices? Will the economics of making chips have to change fundamentally? How are we going to provide power for all of these things? Do we need new protocols and standards? How about circuits? This talk will consider impediments to achieving the terascale and what engineers should be thinking about now to make sure that we can get to the terascale sooner than later.
Thomas Lee received his degrees from MIT, where his 1989 thesis described the world's first CMOS radio. He has been at Stanford since 1994, having previously worked at Analog Devices, Rambus and other companies. He's helped design PLLs for several microprocessors (notably AMD's K6-K7-K8 and DEC's StrongARM), and has founded or cofounded several companies, including the first 3D memory company, Matrix Semiconductor (acquired by Sandisk), and IoE companies ZeroG Wireless (acquired by Microchip) and Ayla Networks. He is an IEEE and Packard Foundation Fellow, has won "Best Paper" awards at CICC and ISSCC, was awarded the 2011 Ho-Am Prize in Engineering and an honorary doctorate from the University of Waterloo. He is on the board of Xilinx, served as Director of DARPA's Microsystems Technology Office, holds ~60 patents, and authored several textbooks. He owns 150-200 oscilloscopes, thousands of vacuum tubes, and kilograms many of obsolete semiconductors. No one, including himself, quite knows why.
Giovanni De Micheli
New trends is electronic systems: Technology, circuits and architectures
This talk will address the needs of new emerging technologies, such as 2-dimensional nanoelectronics, optical devices and quantum devices in terms of design support through computer aids. I will present the circuit abstractions, as well and design methods to achieve competitive circuits.
I will show where existing tools and flows can be used and where new algorithms and data structures are needed in the search of the best match between devices and architectures. I will conclude with some examples of emerging designs.
Giovanni De Micheli is Professor and Director of the Institute of Electrical Engineering and of the Integrated Systems Centre at EPF Lausanne, Switzerland. He is program leader of the Nano-Tera.ch program. Previously, he was Professor of Electrical Engineering at Stanford University.He holds a Nuclear Engineer degree (Politecnico di Milano, 1979), a M.S. and a Ph.D. degree in Electrical Engineering and Computer Science (University of California at Berkeley, 1980 and 1983).
Prof. De Micheli is a Fellow of ACM and IEEE, a member of the Academia Europaea and an International Honorary member of the American Academy of Arts and Sciences. His research interests include several aspects of design technologies for integrated circuits and systems, such as synthesis for emerging technologies, networks on chips and 3D integration. He is also interested in heterogeneous platform design including electrical components and biosensors, as well as in data processing of biomedical information. He is author of: Synthesis and Optimization of Digital Circuits, McGraw-Hill, 1994, co-author and/or co-editor of eight other books and of over 800 technical articles. His citation h-index is 93 according to Google Scholar. He is member of the Scientific Advisory Board of IMEC (Leuven, B), CfAED (Dresden, D) and STMicroelectronics.
Energy Efficient Resilient and Adaptive Circuits
Resilient and adaptive circuit techniques enable architectures that are tolerant to static and dynamic variations such as process variation, voltage droops, temperature and aging. These circuit techniques are key to reducing voltage, temperature and reliability guardbands. Guardbands are used to guarantee that systems will operate correctly on the field when subjected to variations under different workloads and operating environments. However, guardbands incur in significant loss in performance, energy efficiency and also impact the reliability of the system.
In this tutorial we will explore resilient circuit techniques used in modern microprocessors and SoCs. We will start by breaking down the different components of the guardband stack and follow up with a discussion of resilient circuits that mitigate them. We will cover resilient circuit techniques from in-situ detection and correction sequential logic to embedded critical path replica circuits to monitor timing margin. In addition, we will analyze recent advances in adaptive clocking systems and guardband-aware voltage regulation control systems.
Carlos Tokunaga is a Senior Staff Research Scientist and leads the Reliability and Resiliency Circuit Technology Group at the Circuit Research Laboratory at Intel Corporation.
Carlos received the B.S. degree in electronics engineering from the University of Los Andes, Bogotá, Colombia, in 2001, and the M.S. and Ph.D. degrees in electrical engineering from the University of Michigan, Ann Arbor, MI, USA, in 2005 and 2008, respectively. He is currently an IEEE Senior Member.
He has served in the Technical Program Committees of GLSVLSI, ISLPED, HOST, CICC and VLSI Symposium. He has published over 40 technical papers in refereed conferences and journals and has received 13 patents.
Non-volatile Storage Controllers
This tutorial will provide an overview of the key design considerations and architectural implementations for controllers used for non-volatile storage. We will begin with a brief overview of the different classes of non-volatile storage devices, including magnetic hard drives, flash memory, and emerging non-volatile memory.
An objective in the design of a controller is to provide the host computer with a simplified interface to the device. This requires that the designer understand the underlying characteristics of the storage media, and implement a set of algorithms to hide the complexity of the media programming and retrieval. We begin this process by discussing the characteristics of Flash NAND storage, including the organization of the Flash NAND die, the storage and retrieval of multiple bits per memory cell, as well as the wear, ageing, thermal effects, and error coding and correction (ECC). From there, we explore the industry transition from 2D to 3D chip architecture and its implications on device complexity.
The next step in the controller design exploration is the logical to physical translation layer that permits us to re-arrange the data within the device. We then discuss the design of the controller system-on-a-chip (SOC) including processor hierarchies, parallelism of operations, queuing and automation. Next, we cover the internal datapath for read and write operations, and we review the role of several peripherals in the controller system. We close with an overview of the host interface characteristics.
Moving on from Flash Memory, we will review three emerging non-volatile memory classes: phase change memory (PCM), resistive RAM (RRAM), and magnetoresistive RAM (MRAM). The write-in-place nature of these memory types along with the small access sizes, introduce several architectural differences, which we describe further. Finally, we discuss the new host interface protocols under development for these new memories.
We close the tutorial with an overview of industry trends, and projections for future growth.
Mike Moser is a Senior Technologist at Western Digital Corporation in Milpitas, CA, USA. He has over 30 years’ experience in the storage industry, the last ten of which have been in the architecture of Solid State Drives (SSDs) and storage systems. He led the architecture team responsible for the recently announced Western Digital Black NVMe SSD, and participated in the partnership between SanDisk and HP Enterprise to develop emerging memory devices. His most recent work is on the design of Computational Storage systems.
Mike has a Ph.D. in Applied Mechanics from Caltech, and an Sc.B. in Mechanical Engineering from Brown University. He completed his high school in Bogotá, Colombia and is fluent in Spanish.
Circuit Design for Ultrasound on a Chip
As a step-up from the 200-year-old stethoscope, a point-of-care ultrasound imaging device provides a window into the human body without any ionizing radiation. At the heart of such a device is a highly-integrated semiconductor chip, which is the key enabler of the compact form factor, the high bandwidth for multi-modal versatility, and the low power consumption.
The talk will first introduce the basics of medical ultrasound and ultrasonic beam-formation. There will be particular focus on the integration of MEMS ultrasonic transducers in CMOS, which offer superior bandwidth when compared traditional transducer technologies. After that, analog and digital front-end circuit blocks will be discussed, including their design strategies and challenges in expanding them into a large array. The talk will conclude with a brief overview of the Butterfly iQ™ and its Ultrasound-on-Chip™ technology. It is the first FDA cleared, "one probe, whole body imaging" medical ultrasound device, that directly plugs into an iPhone, and at a 50-fold lower price tag than existing solutions.
I am co-founder and IC Design Lead at Butterfly Network, Inc.
, where I developed the Ultrasound-on-Chip technology behind the Butterfly iQ, the world's first "whole body imager".
In 2010, I received a dual S.B in EECS and Mathematics with a minor in Physics from MIT. In 2011 I receive a M.Eng. in EECS, where I developed computational hardware and software for a novel radio telescope concept. I am a Hertz Fellow, a Forbes 30 Under 30 Honoree
in Science, and have been granted 33 patents.
My expertise is in system design; mixed signal design and simulation; digital design and implementation; software engineering; and system integration.
Márcio Cherem Schneider
Modeling and design of ultra-low-voltage CMOS circuits
Ultra-low-voltage (ULV) circuits have gained considerable attention in recent years because of the emergence of small batteries and self-powered applications.
Theoretically, the minimum supply voltage for the proper operation of a CMOS inverter is 2 (ln2) (kT/q) = 36 mV at room temperature. In this tutorial we analyze both the CMOS inverter and the Schmitt Trigger circuit in weak inversion operation, and discuss circuit techniques to approach the theoretical low voltage limit.
For analog circuits the minimum supply voltage has been usually considered higher than the minimum necessary for the operation of digital circuits. In this tutorial, we will present analog circuits such as rectifiers and oscillators that can operate from supply voltages below (kT/q).
Essential to the design of ULV circuits is an understanding of the transistor model and the meaning of its main parameters. We will review ultra-low-power circuits that allow the automatic extraction of the specific current IS and the threshold voltage VT of MOS transistors, which are fundamental parameters for circuit design and testing, as well as for technology characterization.
In the lecture we will discuss key issues for ULV circuits, such as MOS transistors with near zero threshold voltage, process and temperature variation of transistor parameters, and modeling features. A minimalistic ULV standard cell family and a section on ULV circuits for energy harvesting are also included.
studied engineering sciences at the University of the Republic, Montevideo, Uruguay, and electronic engineering at the National Polytechnic School of Grenoble (INPG), France. He received an engineering degree in electronics in 1979 and a doctorate degree in 1982, both from INPG. From 1982 to 1989 he was with the University of São Paulo, Brazil. Since 1990, he has been with the Electrical Engineering Department, Federal University of Santa Catarina, Florianópolis, Brazil where he is now a professor. In the second semester of the academic year 1997/98 he was a research associate with the Analog Mixed Signal Group, Texas A&M University. In the academic year 2008/09 he was a visiting scholar at UC Berkeley.
Márcio Cherem Schneider
received the B.E. and M.S. degrees in electrical engineering from the Federal University of Santa Catarina (UFSC), Brazil, in 1975 and 1980, respectively, and the Ph.D. degree in electrical engineering from the University of São Paulo, São Paulo, Brazil, in 1984. In 1976 he joined the Electrical Engineering Department of UFSC, where he is now a Professor. In 1995, he spent a one-year sabbatical at the Electronics Laboratory of the Swiss Federal Institute of Technology,Lausanne. In 1997 and 2001, he was a Visiting Associate Professor at Texas A&M University.